The present invention relates to a semiconductor storage device, more specifically to a semiconductor storage device structure which enables highly-integrated DRAMs (Dynamic Random Access Memories) to be fabricated within tiny cell areas and by a small number of fabrication steps, and a method for fabricating the semiconductor storage device structure.
A DRAM is a semiconductor storage device which can be formed of one transistor and one capacitor. Various structures of the DRAM and various methods for fabricating the DRAM have been conventionally studied to fabricate semiconductor storage devices of higher density and higher integration.
FIG. 59 shows a sectional view of the semiconductor storage device described in Japanese Patent Laid-Open Publication No. 176148/1986.
Source diffused layers 24 and drain diffused layers 26 are formed on a semiconductor substrate 10 independent of each other. Gate electrodes 20 are formed, through gate oxide films 16, on parts of the semiconductor substrate 10 between the respective source diffused layers 24 and the respective drain diffused layers 26. Memory cell transistors thus comprising the gate electrodes 20, the source diffused layers 24 and the drain diffused layers 26 are constituted.
On the semiconductor substrate 10 with the memory cell transistors formed thereon there are formed inter-layer insulation film 36 having through-holes 38 which are opened on the drain diffused layers 26 and through-holes 40 which are opened on the source diffused layers 24.
Cylindrical capacitor storage electrodes 46 of polycrystalline silicon are formed on the inside walls of the through-holes 40 and have their bottoms connected to the source diffused layers 24.
Capacitor dielectric films 48 are formed on the inside walls and upper surfaces of the capacitor storage electrodes 46, and parts of the upper surfaces of the source diffused layers 24 exposed inside the through-holes 40.
Capacitor opposed electrodes 54 are formed in the through-holes 40 with the capacitor storage electrodes 46 and the capacitor dielectric films 48 formed thereon, and on the inter-layer insulation film 36. Capacitors thus comprising the capacitor storage electrodes 46, the capacitor dielectric films 48 and the capacitor opposed electrodes 54 are formed.
Polycrystalline silicon is buried in the through-holes 38 and is connected to bit lines 62 through an inter-layer insulation film 53 formed on the capacitor opposed electrodes 54.
Furthermore, a metal wiring layer (not shown) is formed on the top of the bit lines through an inter-layer insulation film (not shown), and a DRAM comprising one-transistor and one-capacitor memory cells is formed.
FIG. 60 shows a sectional view of another semiconductor storage device.
Source diffused layers 24 and drain diffused layers 26 are formed on a semiconductor substrate 10 independent of each other. Gate electrodes 20 are formed, through gate oxide films 16, on parts of the semiconductor substrate 10 between the source diffused layers 24 and the drain diffused layers 26. Memory cell transistors thus comprising the gate electrodes 20, the source diffused layers 24 and the drain diffused layers 26 are constituted.
On the semiconductor substrate 10 with the memory cell transistors formed thereon, there are formed inter-layer insulation film 102 having through-holes 98 which are opened on the drain diffused layers 26 and through-holes 100 which are opened on the source diffused layers 24. Insulation films 42 are formed on the gate electrodes 42, covering the same. Exposed parts of the insulation films in the through-holes 98, 100 are defined by the insulation films 42.
An inter-layer insulation film 36 is formed on the inter-layer insulation film 102. Capacitor storage electrodes 46 of polycrystalline silicon are formed on the inside walls and the bottoms of through-holes 40 formed in the inter-layer insulation film 36. The capacitor storage electrodes 46 are connected to the source diffused layers 24 through polycrystalline silicon films 104 buried in the through-holes 100.
Capacitor dielectric films 48 are formed on the inside surfaces and the upper surfaces of the capacitor storage electrodes 46. Capacitor opposed electrodes 54 are formed in the through-holes 40 with the capacitor storage electrodes 46 and the capacitor dielectric films 48 formed thereon, and on the inter-layer insulation film 36. Capacitors thus comprising the capacitor storage electrodes 46, the capacitor dielectric films 48 and the capacitor opposed electrodes 54 are formed.
Polycrystalline silicon films 106 are buried in the through-holes 98 and are connected to bit lines 62 formed on the capacitor opposed electrodes 54 through the inter-layer insulation film 53.
A metal wiring layer (not shown) is formed on the bit lines through an inter-layer insulation film (not shown), and a DRAM comprising one-transistor and one-capacitor memory cells is formed.
To form DRAM cells, usually 9 lithography steps are necessary for the LOCOS isolation, the formation of the gate electrodes (word lines), the bit line contact holes, the bit lines, the through-holes for the capacitor storage electrodes, the capacitor storage electrodes, the capacitor opposed electrodes, the through-holes for the metal wiring, and the metal wiring.
In lithography steps, an alignment allowance for the gate electrodes and the bit line contact holes, an alignment allowance for the gate electrodes and the through-holes, and an alignment allowance for the through-holes and the bit lines are necessary, which makes the memory cell area accordingly larger.
To improve this disadvantage, the semiconductor storage device described in Japanese Patent Laid-Open Publication No. 176148/1986 uses the above-described structure, so that the capacitor storage electrodes are formed by self-alignment with the through-holes, whereby the lithography steps are decreased by one step.
In the semiconductor storage device of FIG. 60, the capacitor storage electrodes are formed by self-alignment, and in addition thereto the through-holes 98, 100 are formed by self-alignment with the gate electrodes, whereby no alignment allowances for the gate electrodes and the through-holes for the bit line contact and for the gate electrodes and the through-holes for the capacitor storage electrodes are necessary. This can accordingly decrease the memory cell area.
The fabrication of a semiconductor storage device which can be highly integrated by a smaller number of lithography steps and with smaller alignment allowances has been thus proposed.
In the semiconductor storage device described in the specification of Japanese Patent Laid-Open Publication No. 176148/1986, a polycrystalline silicon film is deposited to form the capacitor storage electrodes 46, concurrently being buried in the through-holes 38, whereby the above-described structure is formed. The reason for completely filling the through-holes is as follows.
As disclosed in the specification, the bit lines 62 are made of aluminium (Al) and they thus are the uppermost wiring layer. In addition, to contact the Al to the source-drains or the gate electrodes for peripheral circuits, it is necessary that the insulation film is etched by a larger thickness than a thickness of the bit line contact. The inter-layer insulation film 36 of the bit line contact, however, has no trace of etching, and it is presumed that the peripheral circuit through-holes as well as the through-holes 38 are completely filled with polycrystalline silicon.
The peripheral circuit through-holes are thus completely filled because a contact resistance of a peripheral circuit greatly affects efficiency of operation speed of the circuit, and preferably the through-holes are completely filled to reduce the contact resistance as much as possible. Accordingly, it is necessary to completely fill the bit line contact through-holes concurrently with filling the peripheral circuit through-holes.
In the semiconductor storage device disclosed in Japanese Patent Laid-Open Publication No. 176148/1986, the polycrystalline silicon film buried in the peripheral circuit through-holes must be thicker than a through-hole diameter. This is because since the capacitor storage electrodes 46 are concurrently formed of the polycrystalline silicon, the polycrystalline silicon film of an excessive thickness will decrease an inside wall area of the through-holes 40, with a result of a decreased cell capacitance.
When the through-holes 38, 40 are formed, an alignment allowance for the gate electrodes 20 must be taken into consideration. This increases a cell area and decreases a capacitor forming part.
In the semiconductor storage device of FIG. 60, as described above, the self-alignment contact is formed, and in forming the through-holes 98, 100 it is not necessary to consider an alignment allowance for aligning the through-holes 98, 100 with the gate electrode 20. The through-holes 40 and the bit line contact hole 58 are formed separately from each other, and the bit line contact holes are not filled with polycrystalline silicon. Accordingly, a capacitance does not decrease, as is described in the semiconductor storage device described in Japanese Patent Laid-Open Publication No. 176148/1986.
In the semiconductor storage device of FIG. 60, polycrystalline silicon is buried in the through-holes 98, 100 to connect the source diffused layers 24 to the capacitor storage electrodes 46, and the drain diffused layers 26 to the bit lines 62, and an extra lithography step of opening the filled through-holes 98, 100 is needed. In comparison with the semiconductor storage device described in Japanese Patent Laid-Open Publication No. 176148/1986, one lithography step is added.